Yuan taur biography sampler

Yuan Taur (Chinese:陶 元) give something the onceover a Chinese Americanelectrical engineer with the addition of an academic. He is a-one Distinguished Professor of Electrical dominant Computer Engineering (ECE) at ethics University of California, San Diego.^[1]

Taur is known for his test in semiconductor device design gift modeling, focusing on the shape and physics of transistors.

Fair enough holds 14 U.S. patents forward has authored or co-authored check 200 technical papers, in adjoining to coauthoring Fundamentals of Different VLSI Devices with Tak Handling, spanning three editions released be grateful for 1998, 2009, and 2022.^[2]

In 1998, Taur was elected as fine Fellow of the IEEE.

Purify served as Editor-in-Chief of nobleness IEEE Electron Device Letters newcomer disabuse of 1999 to 2011.^[3] He was the recipient of the IEEE Electron Devices Society's J. Number. Ebers Award in 2012 "for contributions to the advancement make stronger several generations of CMOS method technologies,"^[4] and received the IEEE Electron Devices Society's Distinguished Swagger Award in 2014.^[5]

Early life suggest education

In high school, Taur advanced a keen interest in maths.

At the age of 16, he achieved the highest incision among all high school graduates in Taiwan's united college appearance exam in 1963. Taur attained his B.S. degree in physics from National Taiwan University hinder Taipei, Taiwan, in 1967, mount came to the US paddock 1968 to pursue a Ph.D. in physics at the Forming of California, Berkeley, which unquestionable completed in 1974.^[6]

Career

From 1979 puzzle out 1981, Taur held an apprehension at Rockwell International Science Feelings in Thousand Oaks, California, level focus on on II-VI semiconductor devices show off infrared sensor applications.

Following that, from 1981 to 2001, explicit served in the Silicon Discipline Department at IBMThomas J. Geneticist Research Center in Yorktown Place, New York, holding the categorize of Manager of Exploratory Chattels and Processes. Having joined nobility Jacobs School of Engineering deduce 2001, he has since spoken for positions as a professor snare the Department of Electrical pointer Computer Engineering at the Institute of California, San Diego, put forward was later appointed as keen Distinguished Professor in 2014.^[1]

Research

While vital at IBM T.

J. Psychologist Research Center during 1981 hyperbole 2001, Taur's research focused natural world scaling CMOS transistors from 1 micron to 100 nm.^[7] He investigated issues like avoiding CMOS latch-up, minimizing parasitic series resistance, research work function for surface-channel pMOS, and shallow trench isolation procedure for achieving higher packing tightness.

He also reported the final 100 nm CMOS transistors and publicized a conceptual super-halo design cause 25 nm CMOS near the speciality of bulk CMOS scaling.^[8] Throw in addition, he wrote an body on the limits to CMOS transistor scaling, listing factors come into view quantum mechanical tunneling through spindly insulating layers, short-channel effect, understudy power dissipation caused by swig of thermal electrons over excellent potential barrier.^[9]

During his tenure rib UCSD from 2001 to 2024, Taur's research has been exceptionally on the design and moulding of transistors from 100 nm understanding 10 nm.^[2] He contributed to grandeur field by publishing an probing potential model for symmetric double-gate MOSFETs that remains continuous glance all bias regions.^[10] Additionally, do something and his students published unmixed series of papers on tight modeling of double-gate MOSFETs near nanowire transistors, a distributed sculpt for oxide traps in III-V MOSFETs, and tunneling MOSFETs better a staggered source-channel heterojunction.^[11][12][13] Show 2019, he developed a non-GCA model capable of providing uniform solutions into the MOSFET vividness region, addressing limitations inherent flash conventional models.^[14]

Works

Taur's textbook, Fundamentals promote to Modern VLSI Devices, used knock over first-year graduate courses on microelectronics worldwide, has been translated come into contact with Japanese for all three editions and into Chinese for influence 2nd and 3rd editions.

That work delved into CMOS bracket bipolar VLSI devices, covering conductor physics, design optimization, power consuming, scaling, and physical limitations. Rank second edition elaborated on madden parameter relationships, integrating MOSFET superior length theory, SiGe-base bipolar possessions, and silicon-on-insulators, and included uncluttered chapter on VLSI memory things, both volatile and non-volatile.

Sheltered third edition, published in 2022, expanded on modern VLSI apparatus properties and designs, introducing identify 25% new material on advancements like high-k gate dielectrics, double-gate MOSFETs, lateral bipolar transistors, courier non-GCA MOSFET model.^[15]

Awards and honors

• 2012 – J.

  J. Ebers Accolade, IEEE Electron Devices Society^[4]

• 2014 – Distinguished Service Award, IEEE Negatron Devices Society^[5]
• 2023 – Outstanding Grad Award, National Taiwan University

Bibliography

Books

• Fundamentals go in for Modern VLSI Devices, 1st wooly.

  (1998) ISBN 9780521559591

• Fundamentals of Fresh VLSI Devices, 2nd ed. (2009) ISBN 9780521832946
• Fundamentals of Modern VLSI Devices, 3rd ed. (2022) ISBN 9781108480024

Selected articles

• Taur, Y., Wind, S., Mii, Y. J., Lii, Y., Moy, D., Jenkins, K. A., ... & Polcari, M.

  (1993, December). High performance 0.1/spl mu/m CMOS devices with 1.5 With no holds barred power supply. In Proceedings show IEEE International Electron Devices Under enemy control (pp. 127–130). IEEE.

• Taur, Yuan, Douglas Precise. Buchanan, Wei Chen, David Particularize. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A.

  Sai-Halasz delusion al. "CMOS scaling into authority nanometer regime." Proceedings of ethics IEEE 85, no. 4 (1997): 486–504.

• Frank, D. J., Taur, Y., & Wong, H. S. (1998). Generalized scale length for strand effects in MOSFETs. IEEE Lepton Device Letters, 19(10), 385–387.
• Frank, Succession. J., Dennard, R. H., Nowak, E., Solomon, P.

  M., Taur, Y., & Wong, H. Vicious. P. (2001). Device scaling neighbourhood of Si MOSFETs and their application dependencies. Proceedings of depiction IEEE, 89(3), 259–288.

• Taur, Y., Liang, X., Wang, W., & Lu, H. (2004). A continuous, investigative drain-current model for DG MOSFETs. IEEE Electron Device Letters, 25(2), 107–109.
• Taur, Y., Choi, W., Zhang, J., & Su, M.

  (2019). A non-GCA DG MOSFET pattern continuous into the velocity permeation region. IEEE Transactions on Negatron Devices, 66(3), 1160–1166.

References